PIC18F47J53 Datasheet, PDF (146/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

PIC18F47J53 FAMILY
TABLE 10-3: PORTA I/O SUMMARY
Pin
Function
TRIS
Setting
I/O
I/O
Type
Description
RA0/AN0/C1INA/ RA0
ULPWU/PMA6/
RP0
AN0
1
I
TTL PORTA<0> data input; disabled when analog input is enabled.
0
O DIG LATA<0> data output; not affected by analog input.
1
I ANA A/D Input Channel 0 and Comparator C1- input. Default
input configuration on POR; does not affect digital output.
C1INA
1
I ANA Comparator 1 Input A.
ULPWU 1
I ANA Ultra low-power wake-up input.
PMA6⁽¹⁾
x
I/O ST/TTL/ Parallel Master Port digital I/O.
DIG
RP0
1
I
ST Remappable Peripheral Pin 0 input.
0
O DIG Remappable Peripheral Pin 0 output.
RA1/AN1/C2INA/ RA1
VBG/PMA7/RP1
1
I
TTL PORTA<1> data input; disabled when analog input is enabled.
0
O DIG LATA<1> data output; not affected by analog input.
AN1
1
I ANA A/D Input Channel 1 and Comparator C2- input. Default
input configuration on POR; does not affect digital output.
C2INA
1
I ANA Comparator 1 Input A.
VBG
x
PMA7⁽¹⁾
1
O ANA Band Gap Voltage Reference output. (Enabled by setting
the VBGOE bit (WDTCON<4>.)
I ST/TTL Parallel Master Port (io_addr_in[7]).
0
O DIG Parallel Master Port address.
RP1
1
I
ST Remappable Peripheral Pin 1 input.
0
O DIG Remappable Peripheral Pin 1 output
RA2/AN2/C2INB/
C1IND/C3INB/
VREF-/CVREF
RA2
0
O DIG LATA<2> data output; not affected by analog input. Disabled
when CVREF output enabled.
1
I
TTL PORTA<2> data input. Disabled when analog functions are
enabled; disabled when CVREF output is enabled.
AN2
1
I ANA A/D Input Channel 2 and Comparator C2+ input. Default
input configuration on POR; not affected by analog output.
C2INB
1
I ANA Comparator 2 Input B.
0
O ANA CTMU pulse generator charger for the C2INB comparator
input.
C1IND
1
I ANA Comparator 1 Input D.
C3INB
1
VREF-
1
I ANA Comparator 3 Input B.
I ANA A/D and comparator voltage reference low input.
CVREF
x
O ANA Comparator voltage reference output. Enabling this feature
disables digital I/O.
RA3/AN3/C1INB/
VREF+
RA3
0
O DIG LATA<3> data output; not affected by analog input.
1
I
TTL PORTA<3> data input; disabled when analog input is enabled.
AN3
1
I ANA A/D Input Channel 3 and Comparator C1+ input. Default
input configuration on POR.
C1INB
1
I ANA Comparator 1 Input B
VREF+
1
I ANA A/D and comparator voltage reference high input.
Legend:
Note 1:
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level
input/output; x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
This bit is only available on 44-pin devices (PIC18F46J53, PIC18F47J53, PIC18LF46J53 and
PIC18LF47J53).
DS39964B-page 146
Preliminary
 2010 Microchip Technology Inc.