PIC18F47J53 Datasheet, PDF (263/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology

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18.2.3 SOFTWARE INTERRUPT
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCP4IE bit (PIE4<1>) clear to avoid false interrupts
and should clear the flag bit, CCP4IF, following any
such change in operating mode.
18.2.4 CCP PRESCALER
There are four prescaler settings in Capture mode.
They are specified as part of the operating mode
selected by the mode select bits (CCP4M<3:0>).
Whenever the CCP module is turned off, or the CCP
module is not in Capture mode, the prescaler counter
is cleared. This means that any Reset will clear the
prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Doing that also will not clear the
prescaler counter – meaning the first capture may be
from a non-zero prescaler.
Example 18-1 shows the recommended method for
switching between capture prescalers. This example
also clears the prescaler counter and will not generate
the “false” interrupt.
EXAMPLE 18-1: CHANGING BETWEEN
CAPTURE PRESCALERS
CLRF
MOVLW
MOVWF
CCP4CON
NEW_CAPT_PS
CCP4CON
; Turn CCP module off
; Load WREG with the
; new prescaler mode
; value and CCP ON
; Load CCP4CON with
; this value
18.3 Compare Mode
In Compare mode, the 16-bit CCPR4 register value is
constantly compared against either the TMR1 or TMR3
register pair value. When a match occurs, the CCP4
pin can be:
• Driven high
• Driven low
• Toggled (high-to-low or low-to-high)
• Unchanged (that is, reflecting the state of the I/O
latch)
The action on the pin is based on the value of the mode
select bits (CCP4M<3:0>). At the same time, the inter-
rupt flag bit, CCP4IF, is set.
Figure 18-2 gives the Compare mode block diagram
18.3.1 CCP PIN CONFIGURATION
The user must configure the CCPx pin as an output by
clearing the appropriate TRIS bit.
Note:
Clearing the CCP4CON register will force
the RB4 compare output latch (depending
on device configuration) to the default low
level. This is not the PORTB I/O data latch.
18.3.2 TIMER1/3/5 MODE SELECTION
If the CCP module is using the compare feature in
conjunction with any of the Timer1/3/5 timers, the tim-
ers must be running in Timer mode or Synchronized
Counter mode. In Asynchronous Counter mode, the
compare operation may not work.
Note:
Details of the timer assignments for the
CCP modules are given in Table 18-2 and
Table 18-3.
18.3.3 SOFTWARE INTERRUPT MODE
When the Generate Software Interrupt mode is chosen
(CCP4M<3:0> = 1010), the CCP4 pin is not affected.
Only a CCP interrupt is generated, if enabled, and the
CCP4IE bit is set.
18.3.4 SPECIAL EVENT TRIGGER
Both CCP modules are equipped with a Special Event
Trigger. This is an internal hardware signal generated
in Compare mode to trigger actions by other modules.
The Special Event Trigger is enabled by selecting
the Compare Special Event Trigger mode
(CCP4M<3:0> = 1011).
For either CCP module, the Special Event Trigger resets
the Timer register pair for whichever timer resource is
currently assigned as the module’s time base. This
allows the CCPRx registers to serve as a programmable
period register for either timer.
The Special Event Trigger for CCP4 cannot start an
A/D conversion.
Note:
The Special Event Trigger of ECCP1 can
start an A/D conversion, but the A/D
Converter must be enabled. For more
information, see Section 19.0 “Enhanced
Capture/Compare/PWM (ECCP) Module”.
 2010 Microchip Technology Inc.
Preliminary
DS39964B-page 263