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| PIC18F47J53 Datasheet, PDF (366/586 Pages) Microchip Technology – 28/44-Pin, High-Performance USB Microcontrollers with nanoWatt XLP Technology | |||
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PIC18F47J53 FAMILY
21.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical, except in the case of Sleep, or any
Idle mode and bit, SREN, which is a âdonât careâ in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RCxIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 21-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
INTCON
PIR1
PIE1
IPR1
GIE/GIEH
PMPIF(1)
PMPIE(1)
PMPIP(1)
PEIE/GIEL
ADIF
ADIE
ADIP
TMR0IE
RC1IF
RC1IE
RC1IP
INT0IE
TX1IF
TX1IE
TX1IP
RBIE
SSP1IF
SSP1IE
SSP1IP
TMR0IF
CCP1IF
CCP1IE
CCP1IP
INT0IF
TMR2IF
TMR2IE
TMR2IP
PIR3
SSP2IF BCL2IF
RC2IF
TX2IF TMR4IF CTMUIF TMR3GIF
PIE3
SSP2IE BCL2IE RC2IE
TX2IE TMR4IE CTMUIE TMR3GIE
IPR3
SSP2IP BCL2IP RC2IP
TX2IP TMR4IP CTMUIP TMR3GIP
RCSTAx
SPEN
RX9
SREN
CREN ADDEN FERR
OERR
RCREGx
EUSARTx Receive Register
TXSTAx
CSRC
TX9
TXEN
SYNC SENDB BRGH
TRMT
BAUDCONx ABDOVF RCIDL
RXDTP TXCKP BRG16
â
WUE
SPBRGHx EUSARTx Baud Rate Generator High Byte
SPBRGx
EUSARTx Baud Rate Generator Low Byte
Legend: â = unimplemented, read as â0â. Shaded cells are not used for synchronous slave reception.
Note 1: These pins are only available on 44-pin devices.
Bit 0
RBIF
TMR1IF
TMR1IE
TMR1IP
RTCCIF
RTCCIE
RTCCIP
RX9D
TX9D
ABDEN
DS39964B-page 366
Preliminary
ï£ 2010 Microchip Technology Inc.
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