MC9S12KG128 Datasheet, PDF (95/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (FTS128K1ECCV1)
2.3.2.11 Flash Data Registers (FDATA)
The FDATAHI and FDATALO registers are the Flash data registers.
7
6
5
4
3
2
1
0
R
FDATAHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-17. Flash Data High Register (FDATAHI)
7
6
5
4
3
2
1
0
R
FDATALO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-18. Flash Data Low Register (FDATALO)
All FDATAHI and FDATALO bits are readable but are not writable. After an array write as part of a
command write sequence, the FDATA registers will contain the data written. At the completion of a data
compress operation, the resulting 16-bit signature is stored in the FDATA registers. The data compression
signature is readable in the FDATA registers until a new command write sequence is started or a double bit
fault is detected in a Flash array read operation. If a double bit fault is detected during a Flash array read,
erase verify or data compress operation, the parity bits stored in the Flash array at the failed location will
be stored in the lower six bits of FDATALO. The faulty parity bits remain readable until the start of the
next command write sequence.
2.3.2.12 RESERVED2
This register is reserved for factory testing and is not accessible.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-19. RESERVED2
All bits read 0 and are not writable.
2.3.2.13 RESERVED3
This register is reserved for factory testing and is not accessible.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
95