MC9S12KG128 Datasheet, PDF (188/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-5. PLLCTL Field Descriptions (continued)
Field
2
PRE
1
PCE
0
SCME
Description
RTI Enable during Pseudo-Stop Bit — PRE enables the RTI during pseudo-stop mode. Write anytime.
0 RTI stops running during pseudo-stop mode.
1 RTI continues running during pseudo-stop mode.
Note: If the PRE bit is cleared the RTI dividers will go static while pseudo-stop mode is active. The RTI dividers
will not initialize like in wait mode with RTIWAI bit set.
COP Enable during Pseudo-Stop Bit — PCE enables the COP during pseudo-stop mode. Write anytime.
0 COP stops running during pseudo-stop mode
1 COP continues running during pseudo-stop mode
Note: If the PCE bit is cleared the COP dividers will go static while pseudo-stop mode is active. The COP dividers
will not initialize like in wait mode with COPWAI bit set.
Self-Clock Mode Enable Bit — Normal modes: Write once —Special modes: Write anytime — SCME can not
be cleared while operating in self-clock mode (SCM=1).
0 Detection of crystal clock failure causes clock monitor reset (see Section 5.5.1, “Clock Monitor Reset”).
1 Detection of crystal clock failure forces the MCU in self-clock mode (see Section 5.4.7.2, “Self-Clock Mode”).
5.3.2.8 CRG RTI Control Register (RTICTL)
This register selects the timeout period for the real-time interrupt.
7
R
0
W
6
RTR6
5
RTR5
4
RTR4
3
RTR3
2
RTR2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-11. CRG RTI Control Register (RTICTL)
1
RTR1
0
0
RTR0
0
Read: anytime
Write: anytime
NOTE
A write to this register initializes the RTI counter.
Table 5-6. RTICTL Field Descriptions
Field
6:4
RTR[6:4]
3:0
RTR[3:0]
Description
Real-Time Interrupt Prescale Rate Select Bits — These bits select the prescale rate for the RTI. See Table 5-7.
Real-Time Interrupt Modulus Counter Select Bits — These bits select the modulus counter target value to
provide additional granularity. Table 5-7 shows all possible divide values selectable by the RTICTL register. The
source clock for the RTI is OSCCLK.
MC9S12KG128 Data Sheet, Rev. 1.15
188
Freescale Semiconductor