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| MC9S12KG128 Datasheet, PDF (419/600 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 13 Timer Module (TIM16B8CV1)
Read: Anytime
Write: Anytime
Table 13-2. TIOS Field Descriptions
Field
7:0
IOS[7:0]
Description
Input Capture or Output Compare Channel Conï¬guration
0 The corresponding channel acts as an input capture.
1 The corresponding channel acts as an output compare.
13.3.2.2 Timer Compare Force Register (CFORC)
R
W
Reset
7
0
FOC7
0
6
5
4
3
2
0
0
0
0
0
FOC6
FOC5
FOC4
FOC3
FOC2
0
0
0
0
0
Figure 13-7. Timer Compare Force Register (CFORC)
1
0
FOC1
0
0
0
FOC0
0
Read: Anytime but will always return 0x0000 (1 state is transient)
Write: Anytime
Table 13-3. CFORC Field Descriptions
Field
Description
7:0
FOC[7:0]
Force Output Compare Action for Channel 7:0 â A write to this register with the corresponding data bit(s) set
causes the action which is programmed for output compare âxâ to occur immediately. The action taken is the
same as if a successful comparison had just taken place with the TCx register except the interrupt ï¬ag does not
get set.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. If forced output compare on
any channel occurs at the same time as the successful output compare then forced output compare action
will take precedence and interrupt ï¬ag wonât get set.
13.3.2.3 Output Compare 7 Mask Register (OC7M)
R
W
Reset
7
OC7M7
0
Read: Anytime
Write: Anytime
6
OC7M6
5
OC7M5
4
OC7M4
3
OC7M3
2
OC7M2
0
0
0
0
0
Figure 13-8. Output Compare 7 Mask Register (OC7M)
1
OC7M1
0
0
OC7M0
0
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
419
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