MC9S12KG128 Datasheet, PDF (31/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1)
The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop
Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock
circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the
EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic high
a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an input
with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop Controlled
Pierce oscillator circuit on EXTAL and XTAL.
Table 1-4. Clock Selection Based on PE7 During Reset
PE7
Description
1
Loop Controlled Pierce Oscillator selected
0
Full Swing Pierce Oscillator or external clock selected
EXTAL
MCU
XTAL
C7
CRYSTAL OR
CERAMIC
RESONATOR
C8
VSSPLL
Figure 1-6. Loop Controlled Pierce Oscillator Connections (PE7 = 1)
EXTAL
C7
MCU
XTAL
RB
RS*
CRYSTAL OR
CERAMIC
RESONATOR
C8
VSSPLL
* Rs can be zero (shorted) when use with higher frequency crystals.
Refer to manufacturer’s data.
Figure 1-7. Full Swing Pierce Oscillator Connections (PE7 = 0)
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
31