MC9S12KG128 Datasheet, PDF (274/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
Table 9-1. MSCAN Memory Map
Address
Offset
Register
Access
0x0000
0x0001
MSCAN Control Register 0 (CANCTL0)
MSCAN Control Register 1 (CANCTL1)
R/W¹
R/W¹
0x0002 MSCAN Bus Timing Register 0 (CANBTR0)
R/W
0x0003
0x0004
MSCAN Bus Timing Register 1 (CANBTR1)
MSCAN Receiver Flag Register (CANRFLG)
R/W
R/W¹
0x0005
0x0006
0x0007
0x0008
MSCAN Receiver Interrupt Enable Register (CANRIER)
MSCAN Transmitter Flag Register (CANTFLG)
MSCAN Transmitter Interrupt Enable Register (CANTIER)
MSCAN Transmitter Message Abort Request Register (CANTARQ)
R/W
R/W¹
R/W¹
R/W¹
0x0009
0x000A
0x000B
MSCAN Transmitter Message Abort Acknowledge Register (CANTAAK)
MSCAN Transmit Buffer Selection Register (CANTBSEL)
MSCAN Identifier Acceptance Control Register (CANIDAC)
R
R/W¹
R/W¹
0x000C RESERVED
0x000D RESERVED
0x000E MSCAN Receive Error Counter (CANRXERR)
R
0x000F MSCAN Transmit Error Counter (CANTXERR)
R
0x0010 MSCAN Identifier Acceptance Register 0(CANIDAR0)
R/W
0x0011 MSCAN Identifier Acceptance Register 1(CANIDAR1)
R/W
0x0012 MSCAN Identifier Acceptance Register 2 (CANIDAR2)
R/W
0x0013 MSCAN Identifier Acceptance Register 3 (CANIDAR3)
R/W
0x0014 MSCAN Identifier Mask Register 0 (CANIDMR0)
R/W
0x0015 MSCAN Identifier Mask Register 1 (CANIDMR1)
R/W
0x0016 MSCAN Identifier Mask Register 2 (CANIDMR2)
R/W
0x0017 MSCAN Identifier Mask Register 3 (CANIDMR3)
R/W
0x0018 MSCAN Identifier Acceptance Register 4 (CANIDAR4)
R/W
0x0019 MSCAN Identifier Acceptance Register 5 (CANIDAR5)
R/W
0x001A MSCAN Identifier Acceptance Register 6 (CANIDAR6)
R/W
0x001B MSCAN Identifier Acceptance Register 7 (CANIDAR7)
R/W
0x001C MSCAN Identifier Mask Register 4 (CANIDMR4)
R/W
0x001D MSCAN Identifier Mask Register 5 (CANIDMR5)
R/W
0x001E MSCAN Identifier Mask Register 6 (CANIDMR6)
R/W
0x001F
0x0020
-0x002F
0x0030
-0x003F
MSCAN Identifier Mask Register 7 (CANIDMR7)
Foreground Receive Buffer (CANRXFG)
Foreground Transmit Buffer (CANTXFG)
R/W
R²
R²/W
1 _{Refer to detailed register description for write access restrictions on per bit basis.}
2 _{Reserved bits and unused bits within the TX- and RX-buffers (CANTXFG, CANRXFG) will be read}
as “X”, because of RAM-based implementation.
MC9S12KG128 Data Sheet, Rev. 1.15
274
Freescale Semiconductor