MC9S12KG128 Datasheet, PDF (185/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4)
Table 5-2. CRGFLG Field Descriptions (continued)
Field
1
SCMIF
0
SCM
Description
Self-Clock Mode Interrupt Flag — SCMIF is set to 1 when SCM status bit changes. This flag can only be
cleared by writing a 1. Writing a 0 has no effect. If enabled (SCMIE=1), SCMIF causes an interrupt request.
0 No change in SCM bit.
1 SCM bit has changed.
Self-Clock Mode Status Bit — SCM reflects the current clocking mode. Writes have no effect.
0 MCU is operating normally with OSCCLK available.
1 MCU is operating in self-clock mode with OSCCLK in an unknown state. All clocks are derived from PLLCLK
running at its minimum frequency f_SCM.
5.3.2.5 CRG Interrupt Enable Register (CRGINT)
This register enables CRG interrupt requests.
7
6
R
0
RTIE
W
5
4
3
0
0
LOCKIE
2
1
0
0
0
SCMIE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 5-8. CRG Interrupt Enable Register (CRGINT)
Read: anytime
Write: anytime
Table 5-3. CRGINT Field Descriptions
Field
7
RTIE
4
LOCKIE
1
SCMIE
Description
Real-Time Interrupt Enable Bit
0 Interrupt requests from RTI are disabled.
1 Interrupt will be requested whenever RTIF is set.
Lock Interrupt Enable Bit
0 LOCK interrupt requests are disabled.
1 Interrupt will be requested whenever LOCKIF is set.
Self-Clock Mode Interrupt Enable Bit
0 SCM interrupt requests are disabled.
1 Interrupt will be requested whenever SCMIF is set.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
185