MC9S12KG128 Datasheet, PDF (86/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 2 128 Kbyte ECC Flash Module (FTS128K1ECCV1)
Table 2-9. FCNFG Field Descriptions
Field
7
CBEIE
6
CCIE
5
KEYACC
3
DFDIE
Description
Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the Flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see Section 2.3.2.7, “Flash Status Register (FSTAT)”)
is set.
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see Section 2.3.2.7, “Flash Status Register (FSTAT)”)
is set.
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
data.
Double Fault Detect Interrupt Enable — The DFDIE bit enables an interrupt in case a double bit fault is
detected during a Flash block operation.
0 Double bit fault detect interrupt disabled.
1 An interrupt will be requested whenever the DFDIF flag is set (see Section 2.3.2.7, “Flash Status Register
(FSTAT)”).
2.3.2.5 Flash Protection Register (FPROT)
The FPROT register defines which Flash sectors are protected against program or erase operations.
All bits in the FPROT register are readable and writable with restrictions except for RNV[6] which is only
readable (see Section 2.3.2.6, “Flash Protection Restrictions”).
During reset, the FPROT register is loaded from the Flash Configuration Field at address 0xFF0D. To
change the Flash protection that will be loaded during the reset sequence, the upper sector of the Flash
memory must be unprotected, then the Flash Protect/Security byte located as described in Table 2-1 must
be reprogrammed. If the DFDIF flag in the FSTAT register is set while reading the protection field location
during the reset sequence, the FPOPEN bit will be cleared and remaining bits in the FPROT register will
be set to leave the Flash block fully protected.
Trying to alter data in any of the protected areas in the Flash block will result in a protection violation error
and the PVIOL flag will be set in the FSTAT register. A mass erase of the Flash block is not possible if
any of the contained Flash sectors are protected.
MC9S12KG128 Data Sheet, Rev. 1.15
86
Freescale Semiconductor