MC9S12KG128 Datasheet, PDF (168/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.6.3 Port J Data Direction Register (DDRJ)
Module Base + 0x002A
7
6
5
4
3
2
R
0
0
0
0
DDRJ7
DDRJ6
W
Reset
0
0
—
—
—
—
= Unimplemented or Reserved
Figure 4-41. Port J Data Direction Register (DDRJ)
Read: Anytime. Write: Anytime.
1
DDRJ1
0
0
DDRJ0
0
This register configures each port J pin as either input or output.
If enable, CAN4 forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6
(RXCAN4). If CAN4 is disabled, the IIC takes control of the I/O if enabled. In these cases the data
direction bits will not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral module is
disabled.
Table 4-36. Field Descriptions
Field
7, 6, 1, 0 Data Direction Port J
DDRJ[7:6] 0 Associated pin is configured as input.
DDRJ[1:0] 1 Associated pin is configured as output.
Description
4.3.6.4 Port J Reduced Drive Register (RDRJ)
Module Base + 0x002B
7
6
5
4
3
2
R
0
0
0
0
RDRJ7
RDRJ6
W
Reset
0
0
—
—
—
—
= Unimplemented or Reserved
Figure 4-42. Port J Reduced Drive Register (RDRJ)
Read: Anytime. Write: Anytime.
1
RDRJ1
0
0
RDRJ0
0
This register configures the drive strength of each port J output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 4-37. RDRJ Field Descriptions
Field
Description
7, 6, 1, 0 Reduced Drive Port J
RDRJ[7:6] 0 Full drive strength at output.
RDRJ[1:0] 1 Associated pin drives at about 1/6 of the full drive strength.
MC9S12KG128 Data Sheet, Rev. 1.15
168
Freescale Semiconductor