MC9S12KG128 Datasheet, PDF (235/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
Table 7-17. ATDSTAT0 Field Descriptions (continued)
Field
5
ETORF
4
FIFOR
3–0
CC[3:0]
Description
External Trigger Overrun Flag — While in edge trigger mode (ETRIGLE = 0), if additional active edges are
detected while a conversion sequence is in process the overrun flag is set. This flag is cleared when one of the
following occurs:
A) Write “1” to ETORF
B) Write to ATDCTL0,1,2,3,4 (a conversion sequence is aborted)
C) Write to ATDCTL5 (a new conversion sequence is started)
0 No External trigger over run error has occurred
1 External trigger over run error has occurred
FIFO Over Run Flag — This bit indicates that a result register has been written to before its associated
conversion complete flag (CCF) has been cleared. This flag is most useful when using the FIFO mode because
the flag potentially indicates that result registers are out of sync with the input channels. However, it is also
practical for non-FIFO modes, and indicates that a result register has been over written before it has been read
(i.e., the old data has been lost). This flag is cleared when one of the following occurs:
A) Write “1” to FIFOR
B) Start a new conversion sequence (write to ATDCTL5 or external trigger)
0 No over run has occurred
1 Overrun condition exists (result register has been written while associated CCFx flag was still set)
Conversion Counter — These 4 read-only bits are the binary value of the conversion counter. The conversion
counter points to the result register that will receive the result of the current conversion. E.g. CC3 = 0, CC2 = 1,
CC1 = 1, CC0 = 0 indicates that the result of the current conversion will be in ATD Result Register 6. If in
non-FIFO mode (FIFO = 0) the conversion counter is initialized to zero at the begin and end of the conversion
sequence. If in FIFO mode (FIFO = 1) the register counter is not initialized. The conversion counters wraps
around when its maximum value is reached.
7.3.2.8 Reserved Register (ATDTEST0)
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
U
U
U
U
U
U
U
U
W
Reset
1
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-10. Reserved Register (ATDTEST0)
Read: Anytime, returns unpredictable values
Write: Anytime in special modes, unimplemented in normal modes
NOTE
Writing to this registers when in special modes can alter functionality.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
235