MC9S12KG128 Datasheet, PDF (494/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 16 Debug Module (DBGV1)
control (TBC) block. When PAGSEL = 01, registers DBGCAX, DBGCBX, and DBGCCX are used to
match the upper addresses as shown in Table 16-11.
NOTE
If a tagged-type C breakpoint is set at the same address as an A/B
tagged-type trigger (including the initial entry in an inside or outside range
trigger), the C breakpoint will have priority and the trigger will not be
recognized.
16.4.2.1.1 Read or Write Comparison
Read or write comparisons are useful only with TRGSEL = 0, because only opcodes should be tagged as
they are “read” from memory. RWAEN and RWBEN are ignored when TRGSEL = 1.
In full modes (“A and B” and “A and not B”) RWAEN and RWA are used to select read or write
comparisons for both comparators A and B. Table 16-24 shows the effect for RWAEN, RWA, and RW on
the DBGCB comparison conditions. The RWBEN and RWB bits are not used and are ignored in full
modes.
Table 16-24. Read or Write Comparison Logic Table
RWAEN bit
0
0
1
1
1
1
RWA bit
x
x
0
0
1
1
RW signal
0
1
0
1
0
1
Comment
Write data bus
Read data bus
Write data bus
No data bus compare since RW=1
No data bus compare since RW=0
Read data bus
16.4.2.1.2 Trigger Selection
The TRGSEL bit in DBGC1 is used to determine the triggering condition in DBG mode. TRGSEL applies
to both trigger A and B except in the event only trigger modes. By setting TRGSEL, the comparators A
and B will qualify a match with the output of opcode tracking logic and a trigger occurs before the tagged
instruction executes (tagged-type trigger). With the TRGSEL bit cleared, a comparator match forces a
trigger when the matching condition occurs (force-type trigger).
NOTE
If the TRGSEL is set, the address stored in the comparator match address
registers must be an opcode address for the trigger to occur.
16.4.2.2 Trace Buffer Control (TBC)
The TBC is the main controller for the DBG module. Its function is to decide whether data should be stored
in the trace buffer based on the trigger mode and the match signals from the comparator. The TBC also
determines whether a request to break the CPU should occur.
MC9S12KG128 Data Sheet, Rev. 1.15
494
Freescale Semiconductor