MC9S12KG128 Datasheet, PDF (342/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Serial Communications Interface (SCIV1)
NOTE
When queueing an idle character, return the TE bit to logic 1 before the stop
bit of the current frame shifts out through the Tx output signal. Setting TE
after the stop bit appears on Tx output signal causes data previously written
to the SCI data register to be lost. Toggle the TE bit for a queued idle
character while the TDRE flag is set and immediately before writing the
next byte to the SCI data register.
NOTE
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
10.4.4 Receiver
INTERNAL BUS
SBR12–SBR0
SCI DATA REGISTER
BUS
CLOCK
BAUD DIVIDER
RXD
DATA
RECOVERY
11-BIT RECEIVE SHIFT REGISTER
H876543210L
FROM TXD
LOOP
CONTROL
LOOPS
RSRC
RE
RAF
M
WAKE
ILT
WAKEUP
LOGIC
FE
NF
RWU
PE
PE
PARITY
R8
PT
CHECKING
IDLE
IDLE INTERRUPT REQUEST
ILIE
RDRF/OR INTERRUPT REQUEST
RIE
RDRF
OR
Figure 10-12. SCI Receiver Block Diagram
10.4.4.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
MC9S12KG128 Data Sheet, Rev. 1.15
342
Freescale Semiconductor