MC9S12KG128 Datasheet, PDF (586/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
Defining the jitter as:
J(N)
=

max

1
–
t-N-m-----_{⋅-a--t-nx----}(_o--N--m---)
,
1
–
N-t--m---⋅^{--i-t-n-n---(-o-N---m--)-}



NOTE
From the evaluation data a formula for t_max= f(N), resp. t_min = f(N) should
be derived.
Assuming no long term drift of the reference clock, the following will hold
lim J(N) = 0
N→∞
This is very important to notice with respect to timers, serial modules where a pre-scaler will eliminate the
effect of the jitter to a large extent.
Table A-20. PLL Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 P Self Clock Mode frequency
f_SCM
1
—
5.5
MHz
2 D VCO locking range
f_VCO
8
—
50
MHz
3 D Lock Detector transition from Acquisition to Tracking
∆_trk
3%
—
4%¹
—
mode
4 D Lock Detection
∆_Lock
0%
—
1.5%¹
—
5 D Un-Lock Detection
∆_unl
0.5%
—
2.5%¹
—
6 D Lock Detector transition from Tracking to Acquisition
∆_unt
6%
—
8%¹
—
mode
7 C PLLON Total Stabilization delay²
8 D PLLON Acquisition mode stabilization delay²
9 D PLLON Tracking mode stabilization delay²
t_stab
—
0.5
t_acq
—
0.3
t_al
—
0.2
—
ms
—
ms
—
ms
10 D Fitting parameter VCO loop gain
K₁
—
–100
—
MHz/V
11 D Fitting parameter VCO loop frequency
f₁
—
60
—
MHz
12 D Charge pump current acquisition mode
i_ch
—
–38.5
—
µA
13 D Charge pump current tracking mode
14 C Jitter fit parameter 1²
15 C Jitter fit parameter 2²
i_ch
—
–l3.5
—
µA
j₁
—
—
1.1
%
j₂
—
—
0.13
%
1 _{% deviation from target frequency}
2 _{fOSC = 4MHz, fBUS = 25MHz equivalent fVCO = 50MHz: REFDV = #$03, SYNR = #$018, Cs = 4.7nF, Cp = 470pF, Rs = 10KΩ.}
MC9S12KG128 Data Sheet, Rev. 1.15
586
Freescale Semiconductor