MC9S12KG128 Datasheet, PDF (461/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 15 Background Debug Module (BDMV4)
CLOCK
TARGET SYSTEM
HOST
DRIVE TO
BKGD PIN
TARGET SYSTEM
SPEEDUP
PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 15-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
EARLIEST
START OF
NEXT BIT
Figure 15-9 shows the host receiving a logic 0 from the target. Because the host is asynchronous to the
target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of
the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly
drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after
starting the bit time.
CLOCK
TARGET SYS.
HOST
DRIVE TO
BKGD PIN
TARGET SYS.
DRIVE AND
SPEEDUP PULSE
PERCEIVED
START OF BIT TIME
BKGD PIN
HIGH-IMPEDANCE
SPEEDUP PULSE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
Figure 15-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
EARLIEST
START OF
NEXT BIT
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
461