MC9S12KG128 Datasheet, PDF (167/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.6 Port J Registers
Port J is associated with Freescale’s scalable controller area network (CAN4) and Inter-IC bus (IIC)
modules. Each pin is assigned to these modules according to the following priority: CAN4 > IIC >
general-purpose I/O.
The CAN4 function (TXCAN4 and RXCAN4) takes precedence over the IIC and the general purpose I/O
function if the CAN4 module is enabled. Refer to the MSCAN block description chapter for information
on enabling and disabling CAN4.
The IIC function (SCL and SDA) takes precedence over the general purpose I/O function if the IIC is
enabled. If the IIC module takes precedence the SDA and SCL outputs are configured as open drain
outputs. Refer to the IIC block description chapter for information on enabling and disabling the IIC.
During reset, port J pins are configured as inputs with pull-up.
4.3.6.1 Port J I/O Register (PTJ)
Module Base + 0x0028
7
6
5
4
3
2
R
0
0
0
0
PTJ7
PTJ6
W
CAN4 TXCAN4 RXCAN4
IIC SCL
SDA
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 4-39. Port J I/O Register (PTJ)
Read: Anytime. Write: Anytime.
1
PTJ1
0
PTJ0
0
0
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
4.3.6.2 Port J Input Register (PTIJ)
Module Base + 0x0029
7
6
5
4
3
2
R PTIJ7
PTIJ6
0
0
0
0
W
Reset
u
u
0
0
0
0
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-40. Port J Input Register (PTIJ)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIJ1
u
0
PTIJ0
u
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
167