MC9S12KG128 Datasheet, PDF (152/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.3 Port M Registers
Port M is associated with two Freescale’s scalable controller area network (CAN4, CAN0) and one serial
peripheral interface (SPI0) modules. Each pin is assigned to these modules according to the following
priority: CAN0 > CAN4 > SPI0 > general-purpose I/O.
Refer to the SPI block description chapter for information on enabling and disabling the SPI0. Refer to the
MSCAN block description chapter for information on enabling and disabling CAN0 or CAN4. The SPI0,
CAN0 and CAN4 pins can be re-routed. Refer to Section 4.3.3.8, “Module Routing Register (MODRR)”.
During reset, port M pins are configured as high-impedance inputs.
4.3.3.1 Port M I/O Register (PTM)
Module Base + 0x0010
7
R
PTM7
W
6
PTM6
5
PTM5
4
PTM4
3
PTM3
2
PTM2
SPI0
SCK0
MOSI0
SS0
MISO0
CAN4 TXCAN4 RXCAN4 TXCAN4 RXCAN4
CAN0
TXCAN0 RXCAN0 TXCAN0 RXCAN0
Reset
0
0
0
0
0
0
Figure 4-15. Port M I/O Register (PTM)
Read: Anytime. Write: Anytime.
1
PTM1
TXCAN0
0
0
PTM0
RXCAN0
0
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
4.3.3.2 Port M Input Register (PTIM)
Module Base + 0x0011
7
R PTIM7
6
PTIM6
5
PTIM5
4
PTIM4
3
PTIM3
2
PTIM2
W
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-16. Port M Input Register (PTIM)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIM1
u
0
PTIM0
u
MC9S12KG128 Data Sheet, Rev. 1.15
152
Freescale Semiconductor