MC9S12KG128 Datasheet, PDF (196/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4)
of 4 OSCCLK plus 4 PLLCLK cycles to make the transition. During the transition, all clocks freeze and
CPU activity ceases.
CORE CLOCK:
BUS CLOCK / ECLK
Figure 5-18. Core Clock and Bus Clock Relationship
5.4.3 Clock Monitor (CM)
If no OSCCLK edges are detected within a certain time, the clock monitor within the oscillator block
generates a clock monitor fail event. The CRG then asserts self-clock mode or generates a system reset
depending on the state of SCME bit. If the clock monitor is disabled or the presence of clocks is detected
no failure is indicated by the oscillator block.The clock monitor function is enabled/disabled by the CME
control bit.
5.4.4 Clock Quality Checker
The clock monitor performs a coarse check on the incoming clock signal. The clock quality checker
provides a more accurate check in addition to the clock monitor.
A clock quality check is triggered by any of the following events:
• Power-on reset (POR)
• Low voltage reset (LVR)
• Wake-up from full stop mode (exit full stop)
• Clock monitor fail indication (CM fail)
A time window of 50000 VCO clock cycles¹ is called check window.
A number greater equal than 4096 rising OSCCLK edges within a check window is called osc ok. Note that
osc ok immediately terminates the current check window. See Figure 5-19 as an example.
1. VCO clock cycles are generated by the PLL when running at minimum frequency f_SCM.
MC9S12KG128 Data Sheet, Rev. 1.15
196
Freescale Semiconductor