MC9S12KG128 Datasheet, PDF (224/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
Address
Name
0x0022
R
ATDDR9H
W
0x0023
R
ATDDR9L
W
R
0x0024 ATDDR10H
W
0x0025
R
ATDDR10L
W
R
0x0026 ATDDR11H
W
0x0027
R
ATDDR11L
W
R
0x0028 ATDDR12H
W
0x0029
R
ATDDR12L
W
R
0x002A ATDDR13H
W
R
0x002B ATDDR13L
W
R
0x002C ATDDR14H
W
R
0x002D ATDDR14L
W
R
0x002E ATDDR15H
W
0x002F
R
ATDDR15L
W
Bit 7
6
5
4
3
2
1
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
See Section 7.3.2.16.1, “Left Justified Result Data”
and Section 7.3.2.16.2, “Right Justified Result Data”
= Unimplemented or Reserved
Figure 7-2. ATD Register Summary (Sheet 3 of 3)
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Bit 0
MC9S12KG128 Data Sheet, Rev. 1.15
224
Freescale Semiconductor