MC9S12KG128 Datasheet, PDF (193/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Clocks and Reset Generator (CRGV4)
The VCO has a minimum operating frequency, which corresponds to the self-clock mode frequency f_SCM.
EXTAL
XTAL
REDUCED
CONSUMPTION ^OSCCLK
OSCILLATOR
REFDV <3:0>
REFERENCE
LOCK
FEEDBACK DETECTOR
LOCK
REFERENCE
PROGRAMMABLE
DIVIDER
PDET
PHASE
DETECTOR
VDDPLL/VSSPLL
UP
DOWN ^CPUMP
VCO
CRYSTAL
MONITOR
supplied by:
VDDPLL/VSSPLL
VDD/VSS
LOOP
PROGRAMMABLE
DIVIDER
SYN <5:0>
VDDPLL
LOOP
FILTER
XFC
PIN
PLLCLK
Figure 5-16. PLL Functional Diagram
5.4.1.1 PLL Operation
The oscillator output clock signal (OSCCLK) is fed through the reference programmable divider and is
divided in a range of 1 to 16 (REFDV+1) to output the reference clock. The VCO output clock, (PLLCLK)
is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of
[2 x (SYNR +1)] to output the feedback clock. See Figure 5-16.
The phase detector then compares the feedback clock, with the reference clock. Correction pulses are
generated based on the phase difference between the two signals. The loop filter then slightly alters the DC
voltage on the external filter capacitor connected to XFC pin, based on the width and direction of the
correction pulse. The filter can make fast or slow corrections depending on its mode, as described in the
next subsection. The values of the external filter network and the reference frequency determine the speed
of the corrections and the stability of the PLL.
5.4.1.2 Acquisition and Tracking Modes
The lock detector compares the frequencies of the feedback clock, and the reference clock. Therefore, the
speed of the lock detector is directly proportional to the final reference frequency. The circuit determines
the mode of the PLL and the lock condition based on this comparison.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
193