MC9S12KG128 Datasheet, PDF (280/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
9.3.2.3 MSCAN Bus Timing Register 0 (CANBTR0)
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
R
W
Reset:
7
SJW1
0
6
SJW0
5
BRP5
4
BRP4
3
BRP3
2
BRP2
0
0
0
0
0
Figure 9-4. MSCAN Bus Timing Register 0 (CANBTR0)
1
BRP1
0
0
BRP0
0
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 9-5. CANBTR0 Register Field Descriptions
Field
Description
7:6
SJW[1:0]
5:0
BRP[5:0]
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see Table 9-6).
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see Table 9-7).
Table 9-6. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization Jump Width
1 Tq clock cycle
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
Table 9-7. Baud Rate Prescaler
BRP5
0
0
0
0
:
1
BRP4
0
0
0
0
:
1
BRP3
0
0
0
0
:
1
BRP2
0
0
0
0
:
1
BRP1
0
0
1
1
:
1
BRP0
0
1
0
1
:
1
Prescaler value (P)
1
2
3
4
:
64
MC9S12KG128 Data Sheet, Rev. 1.15
280
Freescale Semiconductor