MC9S12KG128 Datasheet, PDF (522/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 18 Multiplexed External Bus Interface (MEBIV3)
18.3.2.7 Data Direction Register E (DDRE)
7
6
5
4
3
2
1
0
R
0
0
Bit 7
6
5
4
3
Bit 2
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 18-11. Data Direction Register E (DDRE)
Read: Anytime when register is in the map
Write: Anytime when register is in the map
Data direction register E is associated with port E. For bits in port E that are configured as general-purpose
I/O lines, DDRE determines the primary direction of each of these pins. A 1 causes the associated bit to
be an output and a 0 causes the associated bit to be an input. Port E bit 1 (associated with IRQ) and bit 0
(associated with XIRQ) cannot be configured as outputs. Port E, bits 1 and 0, can be read regardless of
whether the alternate interrupt function is enabled. The value in a DDR bit also affects the source of data
for reads of the corresponding PORTE register. If the DDR bit is 0 (input) the buffered pin input state is
read. If the DDR bit is 1 (output) the associated port data register bit state is read.
This register is not in the on-chip memory map in expanded and special peripheral modes. Therefore, these
accesses will be echoed externally. Also, it is not in the map in expanded modes while the EME control bit
is set.
Table 18-5. DDRE Field Descriptions
Field
7:2
DDRE
Description
Data Direction Port E
0 Configure the corresponding I/O pin as an input
1 Configure the corresponding I/O pin as an output
Note: It is unwise to write PORTE and DDRE as a word access. If you are changing port E pins from inputs to
outputs, the data may have extra transitions during the write. It is best to initialize PORTE before enabling
as outputs.
MC9S12KG128 Data Sheet, Rev. 1.15
522
Freescale Semiconductor