MC9S12KG128 Datasheet, PDF (145/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.1 Port T Registers
Port T is associated with the 8-channel timer (TIM). Each pin is assigned to these modules according to
the following priority: Timer > general-purpose I/O.
If the timer is enabled, the timer channels configured for output compare are available on port T pins
PT[7:0].
Refer to the TIM block description chapter for information on enabling and disabling the TIM module.
During reset, port T pins are configured as high-impedance inputs.
4.3.1.1 Port T I/O Register (PTT)
Module Base + 0x0000
7
R
PTT7
W
6
PTT6
5
PTT5
4
PTT4
3
PTT3
2
PTT2
Timer IOC7
IOC6
IOC5
IOC4
IOC3
IOC2
Reset
0
0
0
0
0
0
Figure 4-2. Port T I/O Register (PTT))
Read: Anytime. Write: Anytime.
1
PTT1
IOC1
0
0
PTT0
IOC0
0
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port register,
otherwise the value at the pins is read.
4.3.1.2 Port T Input Register (PTIT)
Module Base + 0x0001
7
R PTIT7
6
PTIT6
5
PTIT5
4
PTIT4
3
PTIT3
2
PTIT2
W
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 4-3. Port T Input Register (PTIT)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIT1
u
0
PTIT0
u
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
145