MC9S12KG128 Datasheet, PDF (281/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
9.3.2.4 MSCAN Bus Timing Register 1 (CANBTR1)
The CANBTR1 register configures various CAN bus timing parameters of the MSCAN module.
R
W
Reset:
7
SAMP
0
6
TSEG22
5
TSEG21
4
TSEG20
3
TSEG13
2
TSEG12
1
TSEG11
0
TSEG10
0
0
0
0
0
0
0
Figure 9-5. MSCAN Bus Timing Register 1 (CANBTR1)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Table 9-8. CANBTR1 Register Field Descriptions
Field
Description
7
SAMP
Sampling — This bit determines the number of CAN bus samples taken per bit time.
0 One sample per bit.
1 Three samples per bit¹.
If SAMP = 0, the resulting bit value is equal to the value of the single bit positioned at the sample point. If
SAMP = 1, the resulting bit value is determined by using majority rule on the three total samples. For higher bit
rates, it is recommended that only one sample is taken per bit time (SAMP = 0).
6:4
Time Segment 2 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG2[2:0] of the sample point (see Figure 9-41). Time segment 2 (TSEG2) values are programmable as shown in Table 9-9.
3:0
Time Segment 1 — Time segments within the bit time fix the number of clock cycles per bit time and the location
TSEG1[3:0] of the sample point (see Figure 9-41). Time segment 1 (TSEG1) values are programmable as shown in
Table 9-10.
1 _{In this case, PHASE_SEG1 must be at least 2 time quanta (Tq).}
Table 9-9. Time Segment 2 Values
TSEG22
TSEG21
TSEG20
Time Segment 2
0
0
0
1 Tq clock cycle¹
0
0
1
2 Tq clock cycles
:
:
:
:
1
1
0
7 Tq clock cycles
1
1
1
8 Tq clock cycles
1 _{This setting is not valid. Please refer to Table 9-36 for valid settings.}
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
281