MC9S12KG128 Datasheet, PDF (225/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
7.3.2 Register Descriptions
This section describes in address order all the ATD registers and their individual bits.
7.3.2.1 ATD Control Register 0 (ATDCTL0)
Writes to this register will abort current conversion sequence but will not start a new sequence.
Module Base + 0x0000
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
WRAP3
1
2
WRAP2
1
Figure 7-3. ATD Control Register 0 (ATDCTL0)
1
WRAP1
1
0
WRAP0
1
Read: Anytime
Write: Anytime
Table 7-1. ATDCTL0 Field Descriptions
Field
Description
3–0
Wrap Around Channel Select Bits — These bits determine the channel for wrap around when doing
WRAP[3:0] multi-channel conversions. The coding is summarized in Table 7-2.
WRAP3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Table 7-2. Multi-Channel Wrap Around Coding
WRAP2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
WRAP1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
WRAP0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Multiple Channel Conversions
(MULT = 1) Wrap Around
to AN0/PAD0 After Converting
Reserved
AN1 / PAD1
AN2 / PAD2
AN3 / PAD3
AN4 / PAD4
AN5 / PAD5
AN6 / PAD6
AN7 / PAD7
AN8 / PAD8
AN9 / PAD9
AN10 / PAD10
AN11 / PAD11
AN12 / PAD12
AN13 / PAD13
AN14 / PAD14
AN15 / PAD15
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
225