MC9S12KG128 Datasheet, PDF (581/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
A.7 Reset, Oscillator and PLL
This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and
Phase-Locked-Loop (PLL).
A.7.1 Startup
Table A-18 summarizes several startup characteristics explained in this section. Detailed description of the
startup behavior can be found in the Clock and Reset Generator (CRG) Block User Guide.
Table A-18. Startup Characteristics
Conditions are shown in Table A-4 unless otherwise noted
Num C
Rating
Symbol
Min
Typ
Max
Unit
1 T POR release level
V_PORR
—
—
2.07
V
2 T POR assert level
V_PORA
0.97
—
—
V
3 D Reset input pulse width, minimum input time
PW_RSTL
2
—
—
t_osc
4 D Startup from Reset
n_RST
192
—
196
n_osc
5 D Interrupt pulse width, IRQ edge-sensitive mode
PW_IRQ
20
—
—
ns
6 D Wait recovery startup time
t_WRS
—
—
14
t_cyc
A.7.1.1 POR
The release level V_PORR and the assert level V_PORA are derived from the V_DD Supply. They are also valid
if the device is powered externally. After releasing the POR reset the oscillator and the clock quality check
are started. If after a time t_CQOUT no valid oscillation is detected, the MCU will start using the internal self
clock. The fastest startup time possible is given by n_uposc.
A.7.1.2 SRAM Data Retention
Provided an appropriate external reset signal is applied to the MCU, preventing the CPU from executing
code when VDD5 is out of specification limits, the SRAM contents integrity is guaranteed if after the reset
the PORF bit in the CRG Flags Register has not been set.
A.7.1.3 External Reset
When external reset is asserted for a time greater than PW_RSTL the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
A.7.1.4 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
581