MC9S12KG128 Datasheet, PDF (174/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.5 Resets
The reset values of all registers are given in the Register Description in Section 4.3, “Memory Map and
Register Definition”.
4.5.1 Reset Initialization
All registers including the data registers get set/reset asynchronously. Table 4-44 summarizes the port
properties after reset initialization.
Table 4-44. Port Reset State Summary
Port
T
S
M
P
H
J
Data
Direction
Input
Input
Input
Input
Input
Input
Pull
Mode
Hi-Z
Pull-up
Hi-Z
Hi-Z
Hi-Z
Pull-up
Reset States
Reduced
Drive
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
Wired-OR
Mode
N/A
Disabled
Disabled
N/A
N/A
N/A
Interrupt
N/A
N/A
N/A
Disabled
Disabled
Disabled
4.6 Interrupts
4.6.1 General
Port P, H and J generate a separate edge sensitive interrupt if enabled. Each port offers I/O pins with edge
triggered interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising
or falling edges can be individually configured on per pin basis. All bits/pins per port share the same
interrupt vector. Interrupts can be used with the pins configured as inputs or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or
wait mode.
A digital filter on each pin prevents pulses (Figure 4-49) shorter than a specified time from generating an
interrupt. The minimum time varies over process conditions, temperature and voltage (Figure 4-50 and
Table 4-45).
t_pulse
Figure 4-49. Pulse Illustration
MC9S12KG128 Data Sheet, Rev. 1.15
174
Freescale Semiconductor