MC9S12KG128 Datasheet, PDF (584/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Appendix A Electrical Characteristics
n = ^{f--V--f-r--C-e---Of----} = 2 ⋅ (synr + 1)
= 50
fC
<
----------2-----^â‹---^ζ----^â‹---f--r--e----f---------
π
⋅


ζ
+
1 + ζ²_
⋅
1^--1--0^-
→
fC < ₄--f--r-_â‹--e-₁--f-₀- ;(ζ = 0.9
f_C < 25kHz
)
With the above values the resistance can be calculated. The example is shown for a loop bandwidth
f_C=10kHz:
R = ^2-----â‹---^π---K--^â‹--_Φ-n-----^â‹---f--C--- ^{= 2*π*50*10kHz/(316.7Hz/Ω)=9.9kΩ=~10kΩ}
The capacitance C_s can now be calculated as:
Cs = _π-----2_â‹---f--^â‹_C---^ζ---2_â‹---R--- ≈ _{f-0-C--.--5--â‹}-1--R-6--;(ζ = 0.9) = 5.19nF =~ 4.7nF
The capacitance C_p should be chosen in the range of:
Cs ⁄ 20 ≤ Cp ≤ Cs ⁄ 10 C_p = 470pF
A.7.3.2 Jitter Information
NOTE
This section is under construction
The basic functionality of the PLL is shown in Figure A-3. With each transition of the clock f_cmp, the
deviation from the reference clock f_ref is measured and input voltage to the VCO is adjusted
accordingly.The adjustment is done continuously with no abrupt changes in the clock output frequency.
Noise, voltage, temperature and other factors cause slight variations in the control loop resulting in a clock
jitter. This jitter affects the real minimum and maximum clock periods as illustrated in Figure A-4.
0
1
2
3
N-1
N
t_min1
t_nom
t_max1
t_minN
t_maxN
Figure A-4. Jitter Definitions
MC9S12KG128 Data Sheet, Rev. 1.15
584
Freescale Semiconductor