MC9S12KG128 Datasheet, PDF (67/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 1 MC9S12KG128 Device Overview (MC9S12KG128V1)
1.4 System Clock Description
The Clock and Reset Generator provides the internal clock signals for the core and all peripheral modules.
Figure 1-12 shows the clock connections from the CRG to all modules. Consult the CRG Block Guide for
details on clock generation.
CORE CLOCK
HCS12 CORE
BDM CPU
MEBI MMC
INT DBG
Flash
RAM
EEPROM
EXTAL
XTAL
OSC
BUS CLOCK
CRG
OSCILLATOR CLOCK
TIM
ATD
PWM
SCI0, SCI1
SPI0, SPI1, SPI2
CAN0, CAN4
IIC
PIM
Figure 1-12. Clock Connections
1.5 Modes of Operation
Eight possible modes determine the operating configuration of the MC9S12KG128. Each mode has an
associated default memory map and external bus configuration controlled by a further pin.
Three low power modes exist for the device.
1.5.1 Chip Configuration Summary
The operating mode out of reset is determined by the states of the MODC, MODB, and MODA pins during
reset (Table 1-9). The MODC, MODB, and MODA bits in the MODE register show the current operating
mode and provide limited mode switching during operation. The states of the MODC, MODB, and MODA
pins are latched into these bits on the rising edge of the reset signal. The ROMCTL signal allows the setting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the memory
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
67