MC9S12KG128 Datasheet, PDF (234/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
Table 7-16. Analog Input Channel Select Coding (continued)
CD
CC
CB
0
1
1
0
1
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
CA
Analog Input Channel
0
AN6
1
AN7
0
AN8
1
AN9
0
AN10
1
AN11
0
AN12
1
AN13
0
AN14
1
AN15
7.3.2.7 ATD Status Register 0 (ATDSTAT0)
This read-only register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO
mode, and the conversion counter.
Module Base + 0x0006
7
R
SCF
W
6
5
4
3
2
1
0
0
CC3
CC2
CC1
CC0
ETORF
FIFOR
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-9. ATD Status Register 0 (ATDSTAT0)
Read: Anytime
Write: Anytime (No effect on CC3, CC2, CC1, CC0)
Table 7-17. ATDSTAT0 Field Descriptions
Field
7
SCF
Description
Sequence Complete Flag — This flag is set upon completion of a conversion sequence. If conversion
sequences are continuously performed (SCAN = 1), the flag is set after each one is completed. This flag is
cleared when one of the following occurs:
A) Write “1” to SCF
B) Write to ATDCTL5 (a new conversion sequence is started)
C) If AFFC = 1 and read of a result register
0 Conversion sequence not completed
1 Conversion sequence has completed
MC9S12KG128 Data Sheet, Rev. 1.15
234
Freescale Semiconductor