MC9S12KG128 Datasheet, PDF (395/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 12 Pulse-Width Modulator (PWM8B8CV1)
NOTE
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active duty due to the double
buffering scheme.
See Section 12.4.2.3, “PWM Period and Duty” for more information.
NOTE
Depending on the polarity bit, the duty registers will contain the count of
either the high time or the low time. If the polarity bit is one, the output starts
high and then goes low when the duty count is reached, so the duty registers
contain a count of the high time. If the polarity bit is zero, the output starts
low and then goes high when the duty count is reached, so the duty registers
contain a count of the low time.
To calculate the output duty cycle (high time as a% of period) for a particular channel:
• Polarity = 0 (PPOL x =0)
Duty Cycle = [(PWMPERx-PWMDTYx)/PWMPERx] * 100%
• Polarity = 1 (PPOLx = 1)
Duty Cycle = [PWMDTYx / PWMPERx] * 100%
For boundary case programming values, please refer to Section 12.4.2.8, “PWM Boundary Cases”.
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
1
1
1
1
1
1
1
1
Figure 12-16. PWM Channel Duty Registers (PWMDTYx)
Read: Anytime
Write: Anytime
12.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency
cases. For proper operation, channel 7 must be driven to the active level for a minimum of two bus clocks.
R
W
Reset
7
PWMIF
0
Read: Anytime
Write: Anytime
6
5
4
3
2
0
0
PWM7IN
PWMIE
PWMLVL
PWMRSTRT
0
0
0
0
0
= Unimplemented or Reserved
Figure 12-17. PWM Shutdown Register (PWMSDN)
1
PWM7INL
0
PWM7ENA
0
0
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
395