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MC9S12KG128 Datasheet, PDF (341/600 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Chapter 10 Serial Communications Interface (SCIV1)
If software clears TE while a transmission is in progress (TC = 0), the frame in the transmit shift register
continues to shift out. To avoid accidentally cutting off the last frame in a message, always wait for TDRE
to go high after the last frame before clearing TE.
To separate messages with preambles with minimum idle line time, use this sequence between messages:
1. Write the last byte of the ï¬rst message to SCIDRH/L.
2. Wait for the TDRE ï¬ag to go high, indicating the transfer of the last frame to the transmit shift
register.
3. Queue a preamble by clearing and then setting the TE bit.
4. Write the ï¬rst byte of the second message to SCIDRH/L.
10.4.3.3 Break Characters
Writing a logic 1 to the send break bit, SBK, in SCI control register 2 (SCICR2) loads the transmit shift
register with a break character. A break character contains all logic 0s and has no start, stop, or parity bit.
Break character length depends on the M bit in SCI control register 1 (SCICR1). As long as SBK is at
logic 1, transmitter logic continuously loads break characters into the transmit shift register. After software
clears the SBK bit, the shift register ï¬nishes transmitting the last break character and then transmits at least
one logic 1. The automatic logic 1 at the end of a break character guarantees the recognition of the start bit
of the next frame.
The SCI recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a
logic 0 where the stop bit should be. Receiving a break character has these effects on SCI registers:
⢠Sets the framing error ï¬ag, FE
⢠Sets the receive data register full ï¬ag, RDRF
⢠Clears the SCI data registers (SCIDRH/L)
⢠May set the overrun ï¬ag, OR, noise ï¬ag, NF, parity error ï¬ag, PE, or the receiver active ï¬ag, RAF
(see Section 10.3.2.4, âSCI Status Register 1 (SCISR1)â and Section 10.3.2.5, âSCI Status
Register 2 (SCISR2)â
10.4.3.4 Idle Characters
An idle character contains all logic 1s and has no start, stop, or parity bit. Idle character length depends on
the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle character that begins
the ï¬rst transmission initiated after writing the TE bit from 0 to 1.
If the TE bit is cleared during a transmission, the Tx output signal becomes idle after completion of the
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle
character to be sent after the frame currently being transmitted.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
341
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