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MC9S12KG128 Datasheet, PDF (590/600 Pages) Freescale Semiconductor, Inc – Microcontrollers | |||
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Appendix A Electrical Characteristics
Table A-23. SPI Slave Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
1 P Operating Frequency
1 P SCK Period
2 D Enable Lead Time
3 D Enable Lag Time
4 D Clock (SCK) High or Low Time
5 D Data Setup Time (Inputs)
6 D Data Hold Time (Inputs)
7 D Slave Access Time
8 D Slave MISO Disable Time
9 D Data Valid (after SCK Edge)
10 D Data Hold Time (Outputs)
11 D Rise Time Inputs and Outputs
12 D Fall Time Inputs and Outputs
fop
DC
â
tsck
4
â
tlead
1
â
tlag
1
â
twsck
tcyc â 30
â
tsu
25
â
thi
25
â
ta
â
â
tdis
â
â
tv
â
â
tho
0
â
tr
â
â
tf
â
â
Max
1/4
2048
â
â
â
â
â
1
1
25
â
25
25
Unit
fbus
tbus
tcyc
tcyc
ns
ns
ns
tcyc
tcyc
ns
ns
ns
ns
A.10 External Bus Timing
A timing diagram of the external multiplexed-bus is illustrated in Figure A-9 with the actual timing values
shown on table Table A-24. All major bus signals are included in the diagram. While both a data write and
data read cycle are shown, only one or the other would occur on a particular bus cycle.
A.10.1 General Muxed Bus Timing
The expanded bus timings are highly dependent on the load conditions. The timing parameters shown
assume a balanced load across all outputs.
MC9S12KG128 Data Sheet, Rev. 1.15
590
Freescale Semiconductor
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