MC9S12KG128 Datasheet, PDF (146/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 4 Port Integration Module (PIM9KG128V1)
4.3.1.3 Port T Data Direction Register (DDRT)
Module Base + 0x0002
R
W
Reset
7
DDRT7
0
6
DDRT6
0
5
DDRT5
0
4
DDRT4
0
3
DDRT3
0
2
DDRT2
0
Figure 4-4. Port T Data Direction Register (DDRT)
Read: Anytime. Write: Anytime.
1
DDRT1
0
0
DDRT0
0
This register configures each port T pin as either input or output. The TIM forces the I/O state to be an
output for each timer port associated with an enabled output compare. In these cases the data direction bits
will not change. The DDRT bits revert to controlling the I/O direction of a pin when the associated timer
output compare is disabled. The timer input capture always monitors the state of the pin.
Table 4-3. DDRT Field Descriptions
Field
7–0
Data Direction Port T
DDRT[7:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
4.3.1.4 Port T Reduced Drive Register (RDRT)
Module Base + 0x0003
R
W
Reset
7
RDRT7
0
6
RDRT6
0
5
RDRT5
0
4
RDRT4
0
3
RDRT3
0
2
RDRT2
0
Figure 4-5. Port T Reduced Drive Register (RDRT)
Read: Anytime. Write: Anytime.
1
RDRT1
0
0
RDRT0
0
This register configures the drive strength of each port T output pin as either full or reduced. If the port is
used as input this bit is ignored.
Table 4-4. RDRT Field Descriptions
Field
Description
7–0
Reduced Drive Port T
RDRT[7:0] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
MC9S12KG128 Data Sheet, Rev. 1.15
146
Freescale Semiconductor