MC9S12KG128 Datasheet, PDF (269/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Inter-Integrated Circuit (IICV2)
Clear
IBIF
TX
Tx/Rx
RX
?
Last Byte
Transmitted
Y
?
N
Y
Master
N
Mode
?
Clear IBAL
Y ^Arbitration
Lost
?
N
RXAK=0
?
N
Y
End Of
Y _{Addr Cycle}
(Master Rx)
?
N
Last
Byte To Be Read _Y
?
N
Y
2nd Last
Byte To Be Read
?
N
Write Next
Byte To IBDR
Set TXAK =1
Generate
Stop Signal
N
Y
(Read)
IAAS=1
?
Y
IAAS=1
?
Y
N
Address Transfer
Data Transfer
SRW=1
?
N ^(Write)
TX/RX
RX
?
TX
Set TX
Mode
Write Data
To IBDR
Y ^{ACK From}
Receiver
?
N
Tx Next
Byte
Read Data
From IBDR
And Store
Switch To
Rx Mode
Set RX
Mode
Switch To
Rx Mode
Dummy Read
From IBDR
Generate
Stop Signal
Read Data
From IBDR
And Store
Dummy Read
From IBDR
Dummy Read
From IBDR
RTI
Figure 8-11. Flow-Chart of Typical IIC Interrupt Routine
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
269