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MC9S12KG128 Datasheet, PDF (561/600 Pages) Freescale Semiconductor, Inc – Microcontrollers
Appendix A Electrical Characteristics
Insure external VDD5 load will shunt current greater than maximum injection current. This will be the
greatest risk when the MCU is not consuming power; e.g., if no system clock is present, or if clock rate is
very low which would reduce overall power consumption.
A.1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only. A functional operation under or outside those maxima
is not guaranteed. Stress beyond those limits may affect the reliability or cause permanent damage of the
device.
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (e.g., either VSS5 or VDD5).
Table A-1. Absolute Maximum Ratings
Num
Rating
Symbol
Min
Max
Unit
1 I/O, Regulator and Analog Supply Voltage
2 Internal Logic Supply Voltage1
3 PLL Supply Voltage 1
4 Voltage difference VDDX to VDDR and VDDA
5 Voltage difference VSSX to VSSR and VSSA
6 Digital I/O Input Voltage
7 Analog Reference
8 XFC, EXTAL, XTAL inputs
9 TEST input
10 Instantaneous Maximum Current
Single pin limit for all digital I/O pins 2
VDD5
VDD
VDDPLL
∆VDDX
∆VSSX
VIN
VRH, VRL
VILV
VTEST
ID
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–25
6.5
V
3.0
V
3.0
V
0.3
V
0.3
V
6.5
V
6.5
V
3.0
V
10.0
V
+25
mA
11 Instantaneous Maximum Current
Single pin limit for XFC, EXTAL, XTAL3
IDL
–25
+25
mA
12 Instantaneous Maximum Current
Single pin limit for TEST4
IDT
–0.25
0
mA
13 Operating Temperature Range (packaged)
14 Operating Temperature Range (junction)
TA
–40
125
°C
TJ
–40
140
°C
15 Storage Temperature Range
Tstg
–65
155
°C
1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I/O supply. The absolute
maximum ratings apply when the device is powered from an external source.
2 All digital I/O pins are internally clamped to VSSX and VDDX, VSSR and VDDR or VSSA and VDDA.
3These pins are internally clamped to
4This pin is clamped low to VSSR, but
VSSPLL and VDDPLL
not clamped high. This
pin
must
be
tied
low
in
applications.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
561