MC9S12KG128 Datasheet, PDF (273/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
9.2.2 TXCAN — CAN Transmitter Output Pin
TXCAN is the MSCAN transmitter output pin. The TXCAN output pin represents the logic level on the
CAN bus:
0 = Dominant state
1 = Recessive state
9.2.3 CAN System
A typical CAN system with MSCAN is shown in Figure 9-2. Each CAN station is connected physically
to the CAN bus lines through a transceiver device. The transceiver is capable of driving the large current
needed for the CAN bus and has current protection against defective CAN or defective stations.
CAN node 1
MCU
CAN node 2
CAN node n
CAN Controller
(MSCAN)
TXCAN
RXCAN
Transceiver
CAN_H
CAN_L
CAN Bus
Figure 9-2. CAN System
9.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the MSCAN.
9.3.1 Module Memory Map
Table 9-1 gives an overview on all registers and their individual bits in the MSCAN memory map. The
register address results from the addition of base address and address offset. The base address is
determined at the MCU level and can be found in the Memory block description chapter. The address offset
is defined at the module level.
The MSCAN occupies 64 bytes in the memory space. The base address of the MSCAN module is
determined at the MCU level when the MCU is defined. The register decode map is fixed and begins at the
first address of the module address offset.
Table 9-1 shows the individual registers associated with the MSCAN and their relative offset from the base
address. The detailed register descriptions follow in the order they appear in the register map.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
273