MC9S12KG128 Datasheet, PDF (129/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 3 2 Kbyte EEPROM Module (EETS2KV1)
3.3.2.10 EEPROM Data Register (EDATA)
EDATAHI and EDATALO are the EEPROM data registers.
7
6
5
4
3
2
1
0
R
EDHI
W
Reset
0
0
0
0
0
0
0
0
Figure 3-15. EEPROM Data High Register (EDATAHI)
7
6
5
4
3
2
1
0
R
EDLO
W
Reset
0
0
0
0
0
0
0
0
Figure 3-16. EEPROM Data Low Register (EDATALO)
In normal modes, all EDATAHI and EDATALO bits read 0 and are not writable.
In special modes, all EDATAHI and EDATALO bits are readable and writable.
3.4 Functional Description
3.4.1 Program and Erase Operation
Write and read operations are both used for the program and erase algorithms described in this subsection.
These algorithms are controlled by a state machine whose timebase, EECLK, is derived from the oscillator
clock via a programmable divider. The command register as well as the associated address and data
registers operate as a buffer and a register (2-stage FIFO) so that a new command along with the necessary
data and address can be stored to the buffer while the previous command is remains in progress. The
pipelined operation allows a simplification of command launching. Buffer empty as well as command
completion are signalled by flags in the EEPROM status register. Interrupts for the EEPROM will be
generated if enabled.
The next four subsections describe:
• How to write the ECLKDIV register.
• Command write sequences used to program, erase, and verify the EEPROM memory.
• Valid EEPROM commands.
• Errors resulting from illegal EEPROM operations.
3.4.1.1 Writing the ECLKDIV Register
Prior to issuing any program or erase command, it is first necessary to write the ECLKDIV register to
divide the oscillator down to within 150 kHz to 200 kHz range. The program and erase timings are also a
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
129