MC9S12KG128 Datasheet, PDF (227/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
7.3.2.3 ATD Control Register 2 (ATDCTL2)
This register controls power down, interrupt and external trigger. Writes to this register will abort current
conversion sequence but will not start a new sequence.
Module Base + 0x0002
R
W
Reset
7
ADPU
0
Read: Anytime
Write: Anytime
6
AFFC
5
AWAI
4
ETRIGLE
3
ETRIGP
2
ETRIGE
0
0
0
0
0
= Unimplemented or Reserved
Figure 7-5. ATD Control Register 2 (ATDCTL2)
Table 7-5. ATDCTL2 Field Descriptions
1
ASCIE
0
0
ASCIF
0
Field
7
ADPU
6
AFFC
5
AWAI
4
ETRIGLE
3
ETRIGP
2
ETRIGE
Description
ATD Power Down — This bit provides on/off control over the ATD block allowing reduced MCU power
consumption. Because analog electronic is turned off when powered down, the ATD requires a recovery time
period after ADPU bit is enabled.
0 Power down ATD
1 Normal ATD functionality
ATD Fast Flag Clear All
0 ATD flag clearing operates normally (read the status register ATDSTAT1 before reading the result register to
clear the associate CCF flag).
1 Changes all ATD conversion complete flags to a fast clear sequence. Any access to a result register will cause
the associate CCF flag to clear automatically.
ATD Power Down in Wait Mode — When entering Wait Mode this bit provides on/off control over the ATD block
allowing reduced MCU power. Because analog electronic is turned off when powered down, the ATD requires a
recovery time period after exit from Wait mode.
0 ATD continues to run in Wait mode
1 Halt conversion and power down ATD during Wait mode
After exiting Wait mode with an interrupt conversion will resume. But due to the recovery time the result of this
conversion should be ignored.
External Trigger Level/Edge Control — This bit controls the sensitivity of the external trigger signal. See
Table 7-6 for details.
External Trigger Polarity — This bit controls the polarity of the external trigger signal. See Table 7-6 for details.
External Trigger Mode Enable — This bit enables the external trigger on ETRIG pin or one of the ATD channels
as described in Table 7-4. If external trigger source is one the ATD channels, the digital input buffer of this
channel is enabled. The external trigger allows to synchronize sample and ATD conversions processes with
external events.
0 Disable external trigger
1 Enable external trigger
Note: If using one of the ATD channel as external trigger (ETRIGSEL = 0) the conversion results for this channel
have no meaning while external trigger mode is enabled.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
227