MC9S12KG128 Datasheet, PDF (240/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
7.3.2.14 Port Data Register 0 (PORTAD0)
The data port associated with the ATD is input-only. The port pins are shared with the analog A/D inputs
AN15-8.
Read: Anytime
Write: Anytime, no effect
Module Base + 0x000E
R
W
Reset
Pin
Function
7
PTAD15
1
AN 15
6
PTAD14
5
PTAD13
4
PTAD12
3
PTAD11
2
PTAD10
1
1
1
1
1
AN14
AN13
AN12
AN11
AN10
= Unimplemented or Reserved
Figure 7-16. Port Data Register 0 (PORTAD0)
1
PTAD9
1
AN9
0
PTAD8
1
AN8
The A/D input channels may be used for general-purpose digital input.
Table 7-24. PORTAD0 Field Descriptions
Field
Description
7–0
PTAD[15:0]
A/D Channel x (ANx) Digital Input (x = 15, 14, 13, 12, 11, 10, 9, 8) — If the digital input buffer on the ANx pin
is enabled (IENx = 1) or channel x is enabled as external trigger (ETRIGE = 1, ETRICH[3-0] = x, ETRIGSEL = 0)
read returns the logic level on ANx pin (signal potentials not meeting VIL or VIH specifications will have an
indeterminate value)).
If the digital input buffers are disabled (IENx = 0) and channel x is not enabled as external trigger, read returns
a “1”.
Reset sets all PORTAD0 bits to “1”.
MC9S12KG128 Data Sheet, Rev. 1.15
240
Freescale Semiconductor