MC9S12KG128 Datasheet, PDF (305/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
Section 9.3.2.1, “MSCAN Control Register 0 (CANCTL0)”). The time stamp is written on the bit sample
point for the recessive bit of the ACK delimiter in the CAN frame. In case of a transmission, the CPU can
only read the time stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
R
W
Reset:
7
TSR15
x
6
TSR14
5
TSR13
4
TSR12
3
TSR11
2
TSR10
x
x
x
x
x
Figure 9-34. Time Stamp Register — High Byte (TSRH)
1
TSR9
x
0
TSR8
x
R
W
Reset:
7
TSR7
x
6
TSR6
5
TSR5
4
TSR4
3
TSR3
2
TSR2
x
x
x
x
x
Figure 9-35. Time Stamp Register — Low Byte (TSRL)
1
TSR1
x
0
TSR0
x
Read: Anytime when TXEx flag is set (see Section 9.3.2.7, “MSCAN Transmitter Flag Register
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see Section 9.3.2.11,
“MSCAN Transmit Buffer Selection Register (CANTBSEL)”).
Write: Unimplemented
9.4 Functional Description
9.4.1 General
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
305