MC9S12KG128 Datasheet, PDF (295/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
9.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Module Base + 0x0014 (CANIDMR0)
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
R
W
Reset
7
AM7
0
6
AM6
0
R
W
Reset
7
AM7
0
6
AM6
0
R
W
Reset
7
AM7
0
6
AM6
0
R
W
Reset
7
AM7
0
6
AM6
0
5
AM5
0
5
AM5
0
5
AM5
0
5
AM5
0
4
AM4
0
4
AM4
0
4
AM4
0
4
AM4
0
3
AM3
0
3
AM3
0
3
AM3
0
3
AM3
0
2
AM2
0
2
AM2
0
2
AM2
0
2
AM2
0
1
AM1
0
1
AM1
0
1
AM1
0
1
AM1
0
0
AM0
0
0
AM0
0
0
AM0
0
0
AM0
0
Figure 9-19. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Field
7:0
AM[7:0]
Table 9-23. CANIDMR0–CANIDMR3 Register Field Descriptions
Description
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
295