MC9S12KG128 Datasheet, PDF (420/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 13 Timer Module (TIM16B8CV1)
Table 13-4. OC7M Field Descriptions
Field
Description
7:0
OC7M[7:0]
Output Compare 7 Mask — Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an
output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is
set, the output compare action reflects the corresponding OC7D bit.
13.3.2.4 Output Compare 7 Data Register (OC7D)
R
W
Reset
7
OC7D7
0
6
OC7D6
5
OC7D5
4
OC7D4
3
OC7D3
2
OC7D2
0
0
0
0
0
Figure 13-9. Output Compare 7 Data Register (OC7D)
1
OC7D1
0
0
OC7D0
0
Read: Anytime
Write: Anytime
Table 13-5. OC7D Field Descriptions
Field
Description
7:0
Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register
OC7D[7:0] to transfer to the timer port data register depending on the output compare 7 mask register.
13.3.2.5 Timer Count Register (TCNT)
R
W
Reset
15
TCNT15
0
14
TCNT14
13
TCNT13
12
TCNT12
11
TCNT11
10
TCNT10
0
0
0
0
0
Figure 13-10. Timer Count Register High (TCNTH)
9
TCNT9
0
9
TCNT8
0
R
W
Reset
7
TCNT7
0
6
TCNT6
5
TCNT5
4
TCNT4
3
TCNT3
2
TCNT2
0
0
0
0
0
Figure 13-11. Timer Count Register Low (TCNTL)
1
TCNT1
0
0
TCNT0
0
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
MC9S12KG128 Data Sheet, Rev. 1.15
420
Freescale Semiconductor