MC9S12KG128 Datasheet, PDF (232/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 7 Analog-to-Digital Converter (ATD10B16CV1)
7.3.2.6 ATD Control Register 5 (ATDCTL5)
This register selects the type of conversion sequence and the analog input channels sampled. Writes to this
register will abort current conversion sequence and start a new conversion sequence.
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
DJM
DSGN
SCAN
MULT
CD
CC
CB
CA
W
Reset
0
0
0
0
0
0
0
0
Figure 7-8. ATD Control Register 5 (ATDCTL5)
Read: Anytime
Write: Anytime
Table 7-13. ATDCTL5 Field Descriptions
Field
7
DJM
6
DSGN
5
SCAN
4
MULT
Description
Result Register Data Justification — This bit controls justification of conversion data in the result registers.
See Section 7.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for details.
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned
conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed
data is not available in right justification. See Section 7.3.2.16, “ATD Conversion Result Registers (ATDDRx)” for
details.
0 Unsigned data representation in the result registers.
1 Signed data representation in the result registers.
Table 7-14summarizes the result data formats available and how they are set up using the control bits.
Table 7-15 illustrates the difference between the signed and unsigned, left justified output codes for an input
signal range between 0 and 5.12 Volts.
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the specified
analog input channel for an entire conversion sequence. The analog channel is selected by channel selection
code (control bits CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller samples
across channels. The number of channels sampled is determined by the sequence length value (S8C, S4C, S2C,
S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA control bits);
subsequent channels sampled in the sequence are determined by incrementing the channel selection code or
wrapping around to AN0 (channel 0.
0 Sample only one channel
1 Sample across several channels
MC9S12KG128 Data Sheet, Rev. 1.15
232
Freescale Semiconductor