MC9S12KG128 Datasheet, PDF (175/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Glitch, filtered out, no interrupt flag set
Chapter 4 Port Integration Module (PIM9KG128V1)
Valid pulse, interrupt flag set
t_ifmin
t_ifmax
Figure 4-50. Interrupt Glitch Filter (PPS = 0)
Table 4-45. Pulse Detection Criteria
Pulse
STOP
Mode
STOP¹
Unit
Unit
Ignored
t_pulse <= 3
Bus Clock
t_pulse <= 3.2
µs
Uncertain
3 < t_pulse < 4
Bus Clock 3.2 < t_pulse < 10
µs
Valid
t_pulse >= 4
Bus Clock
t_pulse >= 10
µs
1 _{These values include the spread of the oscillator frequency over temperature,}
voltage and process.
A valid edge on an input is detected if 4 consecutive samples of a passive level are followed by 4
consecutive samples of an active level directly or indirectly.
The filters are continuously clocked by the bus clock in RUN and WAIT mode. In STOP mode the clock
is generated by a single RC oscillator in the port integration module. To maximize current saving the RC
oscillator runs only if the following condition is true on any pin:
Sample count <= 4 and port interrupt enabled (PIE=1) and port interrupt flag not set (PIF=0).
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
175