MC9S12KG128 Datasheet, PDF (443/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
14.5 Resets
This subsection describes how VREG3V3 controls the reset of the MCU.The reset values of registers and
signals are provided in Section 14.3, “Memory Map and Register Definition”. Possible reset sources are
listed in Table 14-4.
Table 14-4. VREG3V3 — Reset Sources
Reset Source
Power-on reset
Low-voltage reset
Local Enable
Always active
Available only in Full Performance Mode
14.5.1 Power-On Reset
During chip power-up the digital core may not work if its supply voltage V_DD is below the POR
deassertion level (V_PORD). Therefore, signal POR which forces the other blocks of the device into reset is
kept high until V_DD exceeds V_PORD. Then POR becomes low and the reset generator of the device
continues the start-up sequence. The power-on reset is active in all operation modes of VREG3V3.
14.5.2 Low-Voltage Reset
For details on low-voltage reset see Section 14.4.6, “LVR — Low-Voltage Reset”.
14.6 Interrupts
This subsection describes all interrupts originated by VREG3V3.
The interrupt vectors requested by VREG3V3 are listed in Table 14-5. Vector addresses and interrupt
priorities are defined at MCU level.
Table 14-5. VREG3V3 — Interrupt Vectors
Interrupt Source
Low Voltage Interrupt (LVI)
Local Enable
LVIE = 1; Available only in Full Performance Mode
14.6.1 LVI — Low-Voltage Interrupt
In FPM VREG3V3 monitors the input voltage V_DDA. Whenever V_DDA drops below level V_LVIA the status
bit LVDS is set to 1. Vice versa, LVDS is reset to 0 when V_DDA rises above level V_LVID. An interrupt,
indicated by flag LVIF = 1, is triggered by any change of the status bit LVDS if interrupt enable bit
LVIE = 1.
NOTE
On entering the Reduced Power Mode, the LVIF is not cleared by the
VREG3V3.
MC9S12KG128 Data Sheet, Rev. 1.15
Freescale Semiconductor
443