MC9S12KG128 Datasheet, PDF (362/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 11 Serial Peripheral Interface (SPIV3)
11.3.2.2 SPI Control Register 2 (SPICR2)
7
6
5
4
3
2
R
0
0
0
0
MODFEN BIDIROE
W
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Read: anytime
Figure 11-4. SPI Control Register 2 (SPICR2)
Write: anytime; writes to the reserved bits have no effect
Table 11-4. SPICR2 Field Descriptions
1
SPISWAI
0
0
SPC0
0
Field
Description
4
MODFEN
3
BIDIROE
1
SPISWAI
0
SPC0
Mode Fault Enable Bit — This bit allows the MODF failure being detected. If the SPI is in master mode and
MODFEN is cleared, then the SS port pin is not used by the SPI. In slave mode, the SS is available only as an
input regardless of the value of MODFEN. For an overview on the impact of the MODFEN bit on the SS port pin
configuration refer to Table 11-3. In master mode, a change of this bit will abort a transmission in progress and
force the SPI system into idle state.
0 SS port pin is not used by the SPI
1 SS port pin with MODF feature
Output Enable in the Bidirectional Mode of Operation — This bit controls the MOSI and MISO output buffer
of the SPI, when in bidirectional mode of operation (SPC0 is set). In master mode this bit controls the output
buffer of the MOSI port, in slave mode it controls the output buffer of the MISO port. In master mode, with SPC0
set, a change of this bit will abort a transmission in progress and force the SPI into idle state.
0 Output buffer disabled
1 Output buffer enabled
SPI Stop in Wait Mode Bit — This bit is used for power conservation while in wait mode.
0 SPI clock operates normally in wait mode
1 Stop SPI clock generation when in wait mode
Serial Pin Control Bit 0 — This bit enables bidirectional pin configurations as shown in Table 11-5. In master
mode, a change of this bit will abort a transmission in progress and force the SPI system into idle state
Pin Mode
Normal
Bidirectional
Normal
Bidirectional
Table 11-5. Bidirectional Pin Configurations
SPC0
0
1
0
1
BIDIROE
MISO
Master Mode of Operation
X
Master In
0
MISO not used by SPI
1
Slave Mode of Operation
X
Slave Out
0
Slave In
1
Slave I/O
MOSI
Master Out
Master In
Master I/O
Slave In
MOSI not used by SPI
MC9S12KG128 Data Sheet, Rev. 1.15
362
Freescale Semiconductor