MC9S12KG128 Datasheet, PDF (326/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 10 Serial Communications Interface (SCIV1)
— Receiver full
— Idle receiver input
— Receiver overrun
— Noise error
— Framing error
— Parity error
• Receiver framing error detection
• Hardware parity checking
• 1/16 bit-time noise detection
10.1.3 Modes of Operation
The SCI operation is the same independent of device resource mapping and bus interface mode. Different
power modes are available to facilitate power saving.
10.1.3.1 Run Mode
Normal mode of operation.
10.1.3.2 Wait Mode
SCI operation in wait mode depends on the state of the SCISWAI bit in the SCI control register 1
(SCICR1).
• If SCISWAI is clear, the SCI operates normally when the CPU is in wait mode.
• If SCISWAI is set, SCI clock generation ceases and the SCI module enters a power-conservation
state when the CPU is in wait mode. Setting SCISWAI does not affect the state of the receiver
enable bit, RE, or the transmitter enable bit, TE.
• If SCISWAI is set, any transmission or reception in progress stops at wait mode entry. The
transmission or reception resumes when either an internal or external interrupt brings the CPU out
of wait mode. Exiting wait mode by reset aborts any transmission or reception in progress and
resets the SCI.
10.1.3.3 Stop Mode
The SCI is inactive during stop mode for reduced power consumption. The STOP instruction does not
affect the SCI register states, but the SCI module clock will be disabled. The SCI operation resumes from
where it left off after an external interrupt brings the CPU out of stop mode. Exiting stop mode by reset
aborts any transmission or reception in progress and resets the SCI.
10.1.4 Block Diagram
Figure 10-1 is a high level block diagram of the SCI module, showing the interaction of various functional
blocks.
MC9S12KG128 Data Sheet, Rev. 1.15
326
Freescale Semiconductor