MC9S12KG128 Datasheet, PDF (282/600 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 9 Freescale’s Scalable Controller Area Network (MSCANV2)
Table 9-10. Time Segment 1 Values
TSEG13
TSEG12
TSEG11
TSEG10
Time segment 1
0
0
0
0
1 Tq clock cycle¹
0
0
0
1
2 Tq clock cycles¹
0
0
1
0
3 Tq clock cycles¹
0
0
1
1
4 Tq clock cycles
:
:
:
:
:
1
1
1
0
15 Tq clock cycles
1
1
1
1
16 Tq clock cycles
1 _{This setting is not valid. Please refer to Table 9-36 for valid settings.}
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in Table 9-9 and Table 9-10).
Eqn. 9-1
Bit Time= ⁽---P----r---e---f-s-C--c---A-a----Nl--e--C-r----L--v--K-a----l--u----e----⁾ • (1 + TimeSegment1 + TimeSegment2)
9.3.2.5 MSCAN Receiver Flag Register (CANRFLG)
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
7
R
WUPIF
W
6
CSCIF
5
RSTAT1
4
RSTAT0
3
TSTAT1
2
TSTAT0
1
OVRIF
0
RXF
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-6. MSCAN Receiver Flag Register (CANRFLG)
NOTE
The CANRFLG register is held in the reset state¹ when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are
read-only; write of 1 clears flag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
MC9S12KG128 Data Sheet, Rev. 1.15
282
Freescale Semiconductor